M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 147

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R
R
M
11.7 INT Interrupt
e
E
3
. v
J
2
Figure 11.10 IFSR Register
0
C
External input generates the INTi interrupt (i = 0 to 5). The LVS bit in the INTiIC register selects either edge
sensitive triggering to generate an interrupt on any edge or level sensitive triggering to generate an inter-
rupt at an applied signal level. The POL bit in the INTiIC register determines the polarity.
For edge sensitive, when the IFSRi bit in the IFSR register is set to "1", an interrupt occurs on both rising
and falling edges of the external input. If the IFSRi bit is set to "1", set the POL bit in the corresponding
register to "0" (falling edge).
For level sensitive, set the IFSRi bit to "0" (single edge). When the INTi pin input level reaches the level set
in the POL bit, the IR bit in the INTiIC register is set to "1". The IR bit remains unchanged even if the INTi
pin level is changed. The IR bit is set to "0" when the INTi interrupt is acknowledged or when the IR bit is
written to "0" by program.
Figure 11.10 shows the IFSR register.
1
9
0 .
8 /
B
0
1
4
______
0
3
G
J
6
u
o r
0 -
. l
External Interrupt Request Source Select Register
b7
NOTES:
u
0
1
, 7
0
p
b6
1
1. Set this bit to "0" to select a level-sensitive triggering.
(
2
M
When setting this bit to "1", set the POL bit in the INTilC register (i = 0 to 5) to "0" (falling edge).
0
b5
0
3
5
2
b4
C
8 /
Page 124
b3
, 4
b2
M
3
b1
2
C
b0
______
f o
8 /
4
4
IFSR7
Symbol
IFSR6
IFSR0
IFSR2
IFSR4
IFSR5
) T
IFSR1
IFSR3
9
Bit
5
Symbol
IFSR
INT0 Interrupt Polarity
Select Bit
INT1 Interrupt Polarity
Select Bit
INT2 Interrupt Polarity
Select Bit
INT3 Interrupt Polarity
Select Bit
INT4 Interrupt Polarity
select bit
INT5 Interrupt Polarity
Select Bit
UART0, UART3
Interrupt Source
Select Bit
UART1, UART4
Interrupt Source
Select Bit
Bit Name
(1)
(1)
(1)
(1)
(1)
(1)
Address
031F
16
_______
0 : UART3 bus conflict, start condition
1 : UART0 bus conflict, start condition
0 : UART4 bus conflict, start condition
1 : UART1 bus conflict, start condition
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
detect, stop condition detect
detect, stop condition detect
detect, stop condition detect
detect, stop condition detect
_______
Function
After Reset
00
16
RW
RW
RW
RW
RW
RW
RW
RW
RW
11. Interrupts
_______