M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 268

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R
R
M
e
E
3
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J
2
Figure 17.32 SIM Interface Format
0
17.7.2 Format
C
1
9
0 .
8 /
B
0
17.7.2.1 Direct Format
17.7.2.2 Inverse Format
1
4
0
3
G
J
parity), the UFORM bit in the UiC0 register to "0" (LSB first) and the UiLCH bit in the UiC1 register to
"0" (not inversed). When data are transmitted, data set in the UiTB register are transmitted with the
even-numbered parity, starting from D
UiRB register, starting from D
UiLCH bit to "1" (inversed). When data are transmitted, values set in the UiTB register are logically
inversed and are transmitted with the odd-numbered parity, starting from D
ceived, received data are logically inversed to be stored in the UiRB register, starting from D
odd-numbered parity determines whether a parity error occurs.
6
Set the PRYE bit to "1", the PRY bit to "0" (odd parity), the UFORM bit to "1" (MSB first) and the
u
Set the PRYE bit in the UiMR register (i=0 to 4) to "1" (parity enabled), the PRY bit to "1" (even
o r
0 -
. l
u
0
1
, 7
0
p
1
(
2
M
0
Transfer Clock
Transfer Clock
0
3
(1) Direct Format
5
2
(2) Inverse Format
C
8 /
Page 245
, 4
TxD
TxD
i=0 to 4
M
i
i
3
2
"H"
"H"
"H"
"H"
"L"
"L"
"L"
"L"
C
f o
8 /
4
4
) T
9
5
0
. The even-numbered parity determines whether a parity error occurs.
D
D
0
7
0.
D
D
1
6
When data are received, received data are stored in the
D
D
2
5
D
D
3
4
D
D
3
4
D
D
2
5
D
D
6
1
D
D
7
0
17. Serial I/O (Special Function)
P : Even parity
P : Odd parity
P
P
7
. When data are re-
7
. The