M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 392

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30845FJGP#U3M30845FJGP
Manufacturer:
TI
Quantity:
18 562
Company:
Part Number:
M30845FJGP#U3
Manufacturer:
MIT
Quantity:
2 367
Company:
Part Number:
M30845FJGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30845FJGP#U3M30845FJGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
M30845FJGP#U3M30845FJGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M
R
R
e
E
3
. v
J
2
0
C
1
9
8 /
0 .
B
0
1
4
23.4.2.1 When the INTSEL Bit is Set to "0"
23.4.2.2 When the INTSEL Bit is Set to "1"
If the CAN-associated interrupt is generated by one of the interrupt request source listed in 23.4.2
CAN0j Interrupts, the corresponding bit in the C0SISTR register is set to "1" (interrupt requested)
when the CAN0 slot k completes a transmission or a reception. The corresponding bit in the C0EISTR
register is set to "1" (interrupt requested) when the CAN0 module detects a bus error, moves into an
error-passive state, or moves into a bus-off state.
The CAN0 interrupt request signal is set to "1" when the corresponding bit in the C0SISTR or C0EISTR
is set to "1" and the corresponding bit in the C0SIMKR or C0EIMKR is set to "1"
When the CAN0 interrupt request signal changes "0" to "1", all CAN0jR bits (j=0 to 2) in the IIO9IR to
IIO11IR registers are set to "1" (interrupt requested).
If at least one of the CAN0jE bits in the IIO9IE to IIO11IE registers is set to "1" (interrupt enabled), the
IR bits in the corresponding CAN0IC to CAN2IC registers are set to "1" (interrupt requested). The
CAN0 interrupt request signal remains set to "1" if another interrupt request source causes a corre-
sponding bit in the C0SISTR or C0EISTR to be set to "1" and the corresponding bit in the C0SIMKR or
C0EIMKR to be set to "1" after the CAN0 interrupt request signal changes "0" to "1". The CAN0jR and
IR bits also remain unchanged.
Bits in the C0SISTR or C0EISTR register and CAN0jR bits (j=0 to 2) in the IIO9IR to IIO11IR registers
are not set to "0" automatically, interrupt acknowledgment notwithstanding. Set these bits to "0" by
program.
The CAN0 interrupts are acknowledged when the CAN0jR bit in the IIO9IR to IIO11IR register and the
corresponding bit in the C0SISTR or C0EISTR register are set to "0". If these bits remain set to "1", all
CAN-associated interrupt request source become invalid.
If the CAN-associated interrupt is generated by one of the interrupt request source listed in 23.3.2
CAN0j Interrupts, the corresponding bit in the C0SISTR register is set to "1" (interrupt requested)
when the CAN0 slot k completes a transmission or a reception. The corresponding bit in the C0EISTR
register is set to "1" (interrupt requested) when the CAN0 module detects a bus error, goes into an
error-passive state, or goes into a bus-off state.
The CAN0 receive interrupt request signal is set to "1" if the corresponding bit in the C0SIMKR register
is set to "1" (interrupt request enabled) and the corresponding bit in the C0SISTR register is set to "1"
when the CAN0 module completes a reception.
The CAN0 transmit interrupt request signal is set to "1" if the corresponding bit in the C0SIMKR regis-
ter is set to "1" and the corresponding bit in the C0SISTR register is set to "1" when the CAN0 module
completes a transmission.
The CAN0 error interrupt request signal is set to "1" if corresponding bits in the C0EIMKR register are
set to "1" and the corresponding bit in the C0EISTR register is set to "1" when the CAN0 module
detects a bus error, goes into an error-passive state, or goes into a bus-off state.
When the CAN0 receive interrupt request signal changes "0" to "1", the CAN00R bit in the IIO9IR
register is set to "1" (interrupt requested). If the CAN00E in the IIO9IE register is set to "1" (interrupt
enabled), the IR bit in the CAN0IC register is set to "1" (interrupt requested).
0
G
3
J
6
u
o r
0 -
. l
u
0
1
p
, 7
0
1
(
2
M
0
3
0
2
5
C
8 /
Page 369
, 4
M
3
2
C
8 /
f o
4
4
) T
9
5
23. CAN Module