M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 165

• Manufacturer Part Number: M30845FJGP#U3
• Description: IC M32C MCU FLASH 512K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30845FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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13.1 Transfer Cycle
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Transfer cycle contains a bus cycle to read data from a memory or the SFR area (source read) and a bus
cycle to write data to a memory space or the SFR area (destination write). The number of read and write
bus cycles depends on source and destination addresses. In memory expansion mode and microprocessor
mode, the number of read and write bus cycles also depends on DS register setting. Software wait state
insertion and the RDY signal make a bus cycle longer.
13.1.1 Effect of Source and Destination Addresses
13.1.2 Effect of the DS Register
13.1.3 Effect of Software Wait State
13.1.4 Effect of RDY Signal
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When a 16-bit data is transferred with a 16-bit data bus and a source address starting with an odd
address, source read cycle is incremented by one bus cycle, compared to a source address starting with
an even address.
When a 16-bit data is transferred with a 16-bit data bus and a destination address starting with an odd
address, a destination write cycle is incremented by one bus cycle, compared to a destination address
starting with an even address.
In an external space in memory expansion or microprocessor mode, transfer cycle varies depending on
the data bus used at the source and destination addresses. See Figure 8.1 for details about the DS
register.
When the SFR area or memory space with software wait states is accessed, the number of CPU clock
cycles is incremented by software wait states.
Figure 13.6 shows an example of a transfer cycle for the source-read bus cycle. In Figure 13.6, the
number of source-read bus cycles is illustrated under different conditions, provided that the destination
address is an address of an external space with the destination-write cycle as two CPU clock cycles
(=one bus cycle). In effect, the destination-write bus cycle is also affected by each condition and the
transfer cycles change accordingly. To calculate a transfer cycle, apply respective conditions to both
destination-write bus cycle and source-read bus cycle. As shown in example (2) of Figure 13.6, when an
8-bit data bus, accessing both source and destination addresses, is used to transfer a 16-bit data, two
bus cycles each are required for the source-read bus cycle and destination-write bus cycle.
In memory expansion or microprocessor mode, the RDY signal affects a bus cycle if a source address or
destination address is allocated address in an external space. Refer to 8.2.6 RDY Signal for details.
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• When an 8-bit data bus (the DSi bit in the DS register is set to "0" (i=0 to 3)), accessing source
• When a 16-bit data bus, accessing source address, and an 8-bit data bus, accessing destination
• When an 8-bit data bus (the DSi bit in the DS register is set to "0" (i=0 to 3)), accessing both source
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address and destination address, is used to transfer a 16-bit data, 8-bit data is transferred twice.
Therefore, two bus cycles are required to read the data and another two bus cycles to write the data.
address, and a 16-bit data bus, accessing destination address, are used to transfer a 16-bit data, 8-
bit data is read twice but is written once as 16-bit data. Therefore, two bus cycles are required for
reading and one bus cycle is for writing.
address, are used to transfer a 16-bit data, 16-bit data is read once and 8-bit data is written twice.
Therefore, one bus cycle is required for reading and two bus cycles is for writing.
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13. DMAC