M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 139

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R
R
M
e
E
3
. v
J
Figure 11.4 Interrupt Control Register (2)
2
0
C
1
9
0 .
8 /
B
11.6.2.1 ILVL2 to ILVL0 Bits
11.6.2.2 IR Bit
0
1
4
0
The ILVL2 to ILVL0 bits determines an interrupt priority level. The higher the interrupt priority level is,
the higher the interrupt priority is.
When an interrupt request is generated, its interrupt priority level is compared to IPL. This interrupt is
acknowledged only when its interrupt priority level is higher than IPL. When the ILVL2 to ILVL0 bits
are set to "000
The IR bit is automatically set to "1" (interrupt requested) when an interrupt request is generated. The
IR bit is automatically set to "0" (no interrupt requested) after an interrupt request is acknowledged and
an interrupt routine in the corresponding interrupt vector is executed.
The IR bit can be set to "0" by program. Do not set to "1".
3
G
J
6
u
o r
0 -
. l
Interrupt Control Register
b7
NOTES:
u
0
1
, 7
0
p
b6
1
1. When a 16-bit data bus is used in microprocessor or memory expansion mode, each INT3 to INT5
2. The IR bit can be set to "0" only (do not set to "1").
3. Set the POL bit to "0" when a corresponding bit in the IFSR register is set to "1" (both edges).
4. When setting the LVS bit to "1" , set a corresponding bit in the IFSR register to "0" (one edge).
(
2
M
pin is used as the data bus. Set the ILVL2 to ILVL0 bits in the INT3IC, INT4IC and INT5IC registers
to "000
0
b5
0
3
5
2
b4
C
8 /
2
2
Page 116
b3
".
" (level 0), its interrupt is ignored.
, 4
b2
M
3
b1
2
C
b0
f o
8 /
4
4
(b7 - b6)
Symbol
) T
ILVL0
ILVL1
ILVL2
9
POL
LVS
Symbol
INT0IC to INT2IC
INT3IC to INT5IC
Bit
5
IR
Interrupt Priority Level
Select Bit
Interrupt Request Bit
Level Sensitive/Edge
Sensitive Switch Bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Polarity Switch Bit
(1)
Bit Name
Address
009E
007C
16
16
, 007E
, 009A
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Requests no interrupt
1 : Requests an interrupt
0 : Selects falling edge or "L"
1 : Selects rising edge or "H"
0 : Edge sensitive
1 : Level sensitive
16
16
, 009C
, 007A
16
16
Function
After Reset
XX00 X000
XX00 X000
(4)
(2)
2
2
(3)
RW
RW
RW
RW
RW
RW
RW
11. Interrupts