M30845FJGP#U3 Renesas Electronics America, M30845FJGP#U3 Datasheet - Page 241

IC M32C MCU FLASH 512K 144LQFP

M30845FJGP#U3

Manufacturer Part Number
M30845FJGP#U3
Description
IC M32C MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30845FJGP#U3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M
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3
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2
Table 17.13 Register Settings in I
0
C
Register
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
IFSR
i=0 to 4
1
9
8 /
0 .
B
0
1
4
0
G
3
J
6
u
o r
0 -
. l
u
0
1
p
, 7
0
1
7 to 0
7 to 0
8
ABT
OER
7 to 0
SMD2 to SMD0
CKDIR
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD, NCH
CKPOL
UFORM
TE
TI
RE
RI
UiRRM, UiLCH,
UiERE
IICM
ABC
BBS
7 to 3
IICM2
CSC
SWC
ALS
STC
SWC2
SDHI
SU1HIM
SSE
CKPH
DINC, NODC, ERR Set to "0"
DL2 to DL0
STAREQ
RSTAREQ
STPREQ
STSPSEL
ACKD
ACKC
SCLHI
SWC9
IFSR6, IFSR7
(
2
M
0
3
0
2
5
C
Bit
8 /
Page 218
, 4
M
3
2
C
8 /
f o
Set transmit data
Received data can be read
ACK or NACK bit can be read
Arbitration lost detect flag
Overrun error flag
Set bit rate
Set to "010
Set to "0"
Set to "0"
Select count source of the UiBRG register
Disabled because the CRD bit is set to "1"
Transfer register empty flag
Set to "1"
Set to "0"
Set to "1"
Set to "1" to enable data transmission
Transfer buffer empty flag
Set to "1" to enable data reception
Reception complete flag
Set to "0"
Set to "1"
Select an arbitration lost detect timing
Bus busy flag
Set to "00000
See Table 17.14
Set to "1" to enable clock synchronization
Set to "1" to fix an "L" signal output from SCLi on the falling edge of the ninth bit
of the transfer clock
Set to "1" to terminate SDAi output when
detecting the arbitration lost
Not used. Set to "0"
Set to "1" for an "L" signal output from SCL forcibly
Set to "1" to disable SDA output
Set to "0"
Set to "0"
See Table 17.14
Set digital delay value
Set to "1" when generating a start condition
Set to "1" when generating a restart condition
Set to "1" when generating a stop condition
Set to "1" when using a condition generating function
Select ACK or NACK
Set to "1" for ACK data output
Set to "1" to enable SCL output stop when
detecting stop condition
Not used. Set to "0"
Set to "1"
4
4
) T
9
5
2
C Mode
2
"
2
"
Master
Function
17. Serial I/O (Special Function)
Disabled
Disabled
Set to "1"
Disabled
Disabled
Set to "0"
Not used. Set to "0"
Set to "1" to reset UARTi
by detecting the start condition
Not used. Set to "0"
Not used. Set to "0"
Set to "1" to fix an "L" signal output
from SCLi on the falling edge of the
ninth bit of the transfer clock
Slave