DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 109

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 2.15 Effective Address Calculation for Branch Instructions
2.8.13
The MOVA instruction stores the effective address in a general register.
1. Firstly, data is obtained by the addressing mode shown in item 2of table 2.14.
2. Next, the effective address is calculated using the obtained data as the index by the addressing
No.
1
2
3
4
5
6
Register indirect
Program-counter relative with 8-bit displacement
Program-counter relative with 16-bit displacement
Program-counter relative with index register
24-bit absolute address
32-bit absolute address
Memory indirect
Extended memory indirect
mode shown in item 5 of table 2.14. The obtained data is used instead of the general register.
The result is stored in a general register. For details, see H8SX Family Software Manual.
Addressing Mode and Instruction Format
op
op
op
op
op
op
MOVA Instruction
disp
op
op
r
r
disp
vec
aa
aa
aa
Effective Address Calculation
31
31
31
31
31
31
31
31
31
31
31
31
31
31
Contents of general register (RL, R, or ER)
Zero
extension
Sign extension
Zero extension
Zero extension
General register contents
Sign extension
23
Zero extension
Memory contents
Memory contents
PC contents
PC contents
PC contents
aa
15
aa
disp
7
1
7
7
disp
aa
vec
2 or 4
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev.1.00 Sep. 08, 2005 Page 59 of 966
×
×
+
+
+
31
31
31
31
31
31
31
31
Effective Address (EA)
REJ09B0219-0100
Section 2 CPU
0
0
0
0
0
0
0
0