DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 454

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
Table 10.5 Input Clock Edge Selection
[Legend]
X: Don't care
Rev.1.00 Sep. 08, 2005 Page 404 of 966
REJ09B0219-0100
Channel
1, 2, 4, 5
CKEG1
0
0
1
Clock Edge Selection
2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
3. In channel 2, the TCNT cannot be cleared by an input capture.
modified.
Bit 7
Reserved
*
0
0
0
0
2
CKEG0
0
1
X
Bit 6
CCLR1
0
1
0
1
Internal Clock
Counted at falling edge
Counted at rising edge
Counted at both edges
Bit 5
CCLR0
0
1
0
1
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture*
TCNT cleared by TGRB compare match/input
capture*
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
Input Clock
3
3
External Clock
Counted at rising edge
Counted at falling edge
Counted at both edges
1