DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 524

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 16-Bit Timer Pulse Unit (TPU)
10.10.5 Conflict between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented. Figure 10.47 shows the timing in this case.
10.10.6 Conflict between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is disabled. A compare match also does not occur when the same
value as before is written.
Figure 10.48 shows the timing in this case.
Rev.1.00 Sep. 08, 2005 Page 474 of 966
REJ09B0219-0100
Figure 10.47 Conflict between TCNT Write and Increment Operations
P
Address
Write
Compare match
signal
TCNT
TGR
P
Address
Write
TCNT input clock
TCNT
Figure 10.48 Conflict between TGR Write and Compare Match
TCNT write data
TGR write data
TCNT write cycle
TGR write cycle
N
TCNT address
N
T
N
TGR address
T
1
1
T
T
2
2
M
N
M
1
Disabled