DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 733

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(2)
The application first analyzes command data from the host in the setup stage, and determines the
subsequent data stage direction. If the result of command data analysis is that the data stage is in-
transfer, one packet of data to be sent to the host is written to the FIFO. If there is more data to be
sent, this data is written to the FIFO after the data written first has been sent to the host (EP0iTS
bit in IFR0 = 1).
The end of the data stage is identified when the host transmits an OUT token and the status stage
is entered.
Note: If the size of the data transmitted by the function is smaller than the data size requested by
Data Stage (Control-In)
the host, the function indicates the end of the data stage by returning to the host a packet
shorter than the maximum packet size. If the size of the data transmitted by the function is
an integral multiple of the maximum packet size, the function indicates the end of the data
stage by transmitting a zero-length packet.
Data transmission to host
Set EP0i transmission
(IFR0.EP0i TS = 1)
IN token reception
Figure 15.11 Data Stage (Control-In) Operation
in EP0i FIFO?
complete flag
USB function
to TRG.EP0s
Valid data
1 written
RDFN?
Yes
Yes
ACK
NACK
NACK
No
No
Interrupt
request
Clear EP0i transmission
data register (EPDR0i)
data register (EPDR0i)
Write 1 to EP0i packet
Write 1 to EP0i packet
(TRG.EP0i PKTE = 1)
(TRG.EP0i PKTE = 1)
Rev.1.00 Sep. 08, 2005 Page 683 of 966
Section 15 USB Function Module (USB)
(IFR0.EP0i TS = 0)
Write data to EP0i
Write data to EP0i
From setup stage
complete flag
Application
enable bit
enable bit
REJ09B0219-0100

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