DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 272

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.13
6.13.1
This LSI has a write data buffer function for the external data bus. Using the write data buffer
function enables internal accesses in parallel with external writes or DMAC single address
transfers. The write data buffer function is made available by setting the WDBE bit to 1 in BCR1.
Figure 6.44 shows an example of the timing when the write data buffer function is used. When this
function is used, if an external address space write or a DMAC single address transfer continues
for two cycles or longer, and there is an internal access next, an external write only is executed in
the first two cycles. However, from the next cycle onward, internal accesses (on-chip memory or
internal I/O register read/write) and the external address space write rather than waiting until it
ends are executed in parallel.
Rev.1.00 Sep. 08, 2005 Page 222 of 966
REJ09B0219-0100
External
space
write
Figure 6.44 Example of Timing when Write Data Buffer Function is Used
Write Data Buffer Function
Write Data Buffer Function for External Data Bus
I
Internal
address bus
B
Address bus
CSn
HHWR, HLWR,
LHWR, LLWR
D15 to D0
T
1
External write cycle
On-chip
memory 1
On-chip memory read
External address
T
2
memory 2
On-chip
Peripheral module address
Peripheral module read
T
3