DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 520

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 16-Bit Timer Pulse Unit (TPU)
(4)
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or
DMAC is activated, the flag is cleared automatically. Figure 10.42 shows the timing for status flag
clearing by the CPU, and figures 10.43 and 10.44 show the timing for status flag clearing by the
DTC or DMAC.
The status flag and interrupt request signal are cleared in synchronization with Pφ after the DTC or
DMAC transfer has started, as shown in figure 10.43. If conflict occurs for clearing the status flag
and interrupt request signal due to activation of multiple DTC or DMAC transfers, it will take up
to five clock cycles (Pφ) for clearing them, as shown in figure 10.44. The next transfer request is
masked for a longer period of either a period until the current transfer ends or a period for five
clock cycles (Pφ) from the beginning of the transfer. Note that in the DTC transfer, the status flag
may be cleared during outputting the destination address.
Rev.1.00 Sep. 08, 2005 Page 470 of 966
REJ09B0219-0100
Status Flag Clearing Timing
P
Address
Write
Status flag
Interrupt request
signal
Figure 10.42 Timing for Status Flag Clearing by CPU
TSR write cycle
TSR address
T
1
T
2