DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 200

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 6 Bus Controller (BSC)
6.3
Figure 6.4 shows the internal bus configuration of this LSI. The internal bus of this LSI consists of
the following three types.
• Internal system bus
• Internal peripheral bus
• External access cycle
Rev.1.00 Sep. 08, 2005 Page 150 of 966
REJ09B0219-0100
A bus that connects the CPU, DTC, DMAC, on-chip RAM, on-chip ROM, internal peripheral
bus, and external access bus.
A bus that accesses registers in the bus controller, interrupt controller, and DMAC, and
registers of peripheral modules such as SCI and timer.
A bus that accesses external devices via the external bus interface.
Bus Configuration
synchronization
Write data
buffer
I
synchronization
P
CPU
Figure 6.4 Internal Bus Configuration
power-down controller
interrupt controller,
Internal peripheral bus
Bus controller,
DTC
Peripheral
functions
On-chip
RAM
Internal system bus
DMAC
On-chip
ROM
synchronization
B
External access bus
External bus
interface
Write data
buffer

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