DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 428

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 I/O Ports
Table 9.5
Rev.1.00 Sep. 08, 2005 Page 378 of 966
REJ09B0219-0100
Port
P1
P2
7
6
5
4
3
2
1
0
7
6
5
Output
Specification
Signal Name
SCL0_OE
DACK1A_OE
SDA0_OE
TEND1A_OE
SCL1_OE
TxD5_OE
IrTxD5_OE
SDA1_OE
—
DACK0A_OE
SCK2_OE
TEND0A_OE
TxD2_OE
TIOCB5_OE
PO7_OE
TIOCA5_OE
TMO1_OE
TxD1_OE
PO6_OE
TIOCA4_OE
PO5_OE
Available Output Signals and Settings in Each Port
Output
Signal
Name
SCL0
DACK1
SDA0
TEND1
SCL1
TxD5
IrTxD5
SDA1
—
DACK0
SCK2
TEND0
TxD2
TIOCB5
PO7
TIOCA5
TMO1
TxD1
PO6
TIOCA4
PO5
Signal Selection
Register Settings
PFCR7.DMAS1[A,B] = 00 DACR.AMS = 1, DMDR.DACKE = 1
PFCR7.DMAS1[A,B] = 00 DMDR.TENDE = 1
—
PFCR7.DMAS0[A,B] = 00 DACR.AMS = 1, DMDR.DACKE = 1
PFCR7.DMAS0[A,B] = 00 DMDR.TENDE = 1
Peripheral Module Settings
ICCRA.ICE = 1
ICCRA.ICE = 1
ICCRA.ICE = 1
SCR.TE = 1, IrCR.IrE = 0
SCR.TE = 1, IrCR.IrE = 1
ICCRA.ICE = 1
—
When SCMR.SMIF = 1:
SCR.TE = 1 or SCR.RE = 1 while
SMR.GM = 0, SCR.CKE [1, 0] = 01 or while
SMR.GM = 1
When SCMR.SMIF = 0:
SCR.TE = 1 or SCR.RE = 1 while
SMR.C/A = 0, SCR.CKE [1, 0] = 01 or while
SMR.C/A = 1, SCR.CKE 1 = 0
SCR.TE = 1
TPU.TIOR5.IOB3 = 0, TPU.TIOR5.IOB[1,0]
= 01/10/11
NDERL.NDER7 = 1
TPU.TIOR5.IOA3 = 0, TPU.TIOR5.IOA[1,0]
= 01/10/11
TCSR.OS3,2 = 01/10/11 or
TCSR.OS[1,0] = 01/10/11
SCR.TE = 1
NDERL.NDER6 = 1
TPU.TIOR4.IOA3 = 0, TPU.TIOR4.IOA[1,0]
= 01/10/11
NDERL.NDER5 = 1