DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 764

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 I
Rev.1.00 Sep. 08, 2005 Page 714 of 966
REJ09B0219-0100
Bit
7
6
5
4
3
Bit Name
TDRE
TEND
RDRF
NACKF
STOP
2
C Bus Interface2 (IIC2)
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Transmit Data Register Empty
[Setting condition]
•
[Clearing conditions]
•
•
Transmit End
[Setting condition]
•
[Clearing conditions]
•
•
Receive Data Register Full
[Setting condition]
•
[Clearing conditions]
•
•
No Acknowledge Detection Flag
[Setting condition]
•
[Clearing condition]
•
Stop Condition Detection Flag
[Setting condition]
•
[Clearing condition]
•
When data is transferred from ICDRT to ICDRS
and ICDRT becomes empty
When 0 is written to this bit after reading TDRE = 1
When data is written to ICDRT
When the ninth clock of SCL rises while the TDRE
flag is 1
When 0 is written to this bit after reading TEND = 1
When data is written to ICDRT
When receive data is transferred from ICDRS to
ICDRR
When 0 is written to this bit after reading RDRF = 1
When data is read from ICDRR
When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER
is set to 1
When 0 is written to this bit after reading NACKF =
1
When a stop condition is detected after frame
transfer
When 0 is written to this bit after reading STOP = 1