DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 21

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.7 Interrupt Sources................................................................................................................ 524
12.8 Usage Notes ....................................................................................................................... 526
Section 13 Watchdog Timer (WDT)..................................................................531
13.1 Features.............................................................................................................................. 531
13.2 Input/Output Pin................................................................................................................. 532
13.3 Register Descriptions ......................................................................................................... 533
13.4 Operation ........................................................................................................................... 536
13.5 Interrupt Source ................................................................................................................. 538
13.6 Usage Notes ....................................................................................................................... 539
Section 14 Serial Communication Interface (SCI, IrDA, CRC).......................543
14.1 Features.............................................................................................................................. 543
14.2 Input/Output Pins ............................................................................................................... 548
14.3 Register Descriptions ......................................................................................................... 549
12.7.1 Interrupt Sources and DTC Activation ................................................................. 524
12.7.2 A/D Converter Activation..................................................................................... 525
12.8.1 Notes on Setting Cycle.......................................................................................... 526
12.8.2 Conflict between TCNT Write and Counter Clear................................................ 526
12.8.3 Conflict between TCNT Write and Increment...................................................... 527
12.8.4 Conflict between TCOR Write and Compare Match ............................................ 527
12.8.5 Conflict between Compare Matches A and B....................................................... 528
12.8.6 Switching of Internal Clocks and TCNT Operation.............................................. 528
12.8.7 Mode Setting with Cascaded Connection ............................................................. 530
12.8.8 Module Stop Mode Setting ................................................................................... 530
12.8.9 Interrupts in Module Stop Mode........................................................................... 530
13.3.1 Timer Counter (TCNT)......................................................................................... 533
13.3.2 Timer Control/Status Register (TCSR)................................................................. 533
13.3.3 Reset Control/Status Register (RSTCSR)............................................................. 535
13.4.1 Watchdog Timer Mode ......................................................................................... 536
13.4.2 Interval Timer Mode............................................................................................. 538
13.6.1 Notes on Register Access...................................................................................... 539
13.6.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 540
13.6.3 Changing Values of Bits CKS2 to CKS0.............................................................. 540
13.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................. 540
13.6.5 Internal Reset in Watchdog Timer Mode.............................................................. 541
13.6.6 System Reset by WDTOVF Signal....................................................................... 541
13.6.7 Transition to Watchdog Timer Mode or Software Standby Mode........................ 541
14.3.1 Receive Shift Register (RSR) ............................................................................... 551
14.3.2 Receive Data Register (RDR) ............................................................................... 551
Rev.1.00 Sep. 08, 2005 Page xix of xlviiil