DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 613

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
5
4
Bit Name
ORER
FER
Initial
Value
0
0
R/W
R/(W)* Overrun Error
R/(W)* Framing Error
Description
Indicates that an overrun error has occurred during
reception and the reception ends abnormally.
[Setting condition]
•
[Clearing condition]
•
Indicates that a framing error has occurred during
reception in asynchronous mode and the reception ends
abnormally.
[Setting condition]
•
[Clearing condition]
•
Section 14 Serial Communication Interface (SCI, IrDA, CRC)
When the next serial reception is completed while
RDRF = 1
In RDR, receive data prior to an overrun error
occurrence is retained, but data received after the
overrun error occurrence is lost. When the ORER flag
is set to 1, subsequent serial reception cannot be
performed. Note that, in clocked synchronous mode,
serial transmission also cannot continue.
When 0 is written to ORER after reading ORER = 1
Even when the RE bit in SCR is cleared, the ORER
flag is not affected and retains its previous value.
When the stop bit is 0
In 2-stop-bit mode, only the first stop bit is checked
whether it is 1 but the second stop bit is not checked.
Note that receive data when the framing error occurs
is transferred to RDR, however, the RDRF flag is not
set. In addition, when the FER flag is being set to 1,
the subsequent serial reception cannot be performed.
In clocked synchronous mode, serial transmission
also cannot continue.
When 0 is written to FER after reading FER = 1
Even when the RE bit in SCR is cleared, the FER flag
is not affected and retains its previous value.
Rev.1.00 Sep. 08, 2005 Page 563 of 966
REJ09B0219-0100