DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 357

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

This LSI includes a data transfer controller (DTC). The DTC can be activated to transfer data by
an interrupt request.
8.1
• Transfer possible over any number of channels:
• Three transfer modes
• Short address mode or full address mode selectable
• Size of data for data transfer can be specified as byte, word, or longword
• A CPU interrupt can be requested for the interrupt that activated the DTC
• Read skip of the transfer information specifiable
• Writeback skip executed for the fixed transfer source and destination addresses
• Module stop mode specifiable
Multiple data transfer enabled for one activation source (chain transfer)
Chain transfer specifiable after data transfer (when the counter is 0)
Normal/repeat/block transfer modes selectable
Transfer source and destination addresses can be selected from increment/decrement/fixed
 Short address mode
 Full address mode
The bus cycle is divided if an odd address is specified for a word or longword transfer.
The bus cycle is divided if address 4n + 2 is specified for a longword transfer.
A CPU interrupt can be requested after one data transfer completion
A CPU interrupt can be requested after the specified data transfer completion
Transfer information is located on a 3-longword boundary
The transfer source and destination addresses can be specified by 24 bits to select a 16-
Mbyte address space directly
Transfer information is located on a 4-longword boundary
The transfer source and destination addresses can be specified by 32 bits to select a 4-
Gbyte address space directly
Features
Section 8 Data Transfer Controller (DTC)
Section 8 Data Transfer Controller (DTC)
Rev.1.00 Sep. 08, 2005 Page 307 of 966
REJ09B0219-0100