DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 901

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5. Figure 21.6 shows the clock modification timing. After a value is written to SCKCR, this LSI
6. When Iφ > Pφ is specified by SCKCR, signals from the peripheral modules must be
21.5.2
Since various characteristics related to the resonator are closely linked to the user's board design,
thorough evaluation is necessary on the user's part, using the resonator connection examples
shown in this section as a reference. As the parameters for the resonator will depend on the
floating capacitance of the resonator and the mounting circuit, the parameters should be
determined in consultation with the resonator manufacturer. The design must ensure that a voltage
exceeding the maximum rating is not applied to the resonator pin.
Bus master
waits for the current bus cycle to complete. After the current bus cycle completes, each clock
frequency will be modified within one cycle (worst case) of the external input clock φ.
synchronized with the system clock. When CPU instructions are used to clear the interrupt
source flag of a peripheral module, the flag must be read after being cleared to 0.
External
clock
I
Notes on Resonator
Operating clock
specified in SCKCR
CPU
Figure 21.6 Clock Modification Timing
after the bus cycle completion
One cycle (worst case)
CPU
Operating clock changed
Rev.1.00 Sep. 08, 2005 Page 851 of 966
Section 21 Clock Pulse Generator
CPU
REJ09B0219-0100