DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 636

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 Serial Communication Interface (SCI, IrDA, CRC)
14.4
Figure 14.5 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), transmit/receive data, a parity bit, and stop bits (high level). In
asynchronous serial communication, the communication line is usually held in the mark state
(high level). The SCI monitors the communication line, and when it goes to the space state (low
level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and
receiver are independent units, enabling full-duplex communication. Both the transmitter and the
receiver also have a double-buffered structure, so that data can be read or written during
transmission or reception, enabling continuous data transmission and reception.
Rev.1.00 Sep. 08, 2005 Page 586 of 966
REJ09B0219-0100
Bit
2
1, 0
Serial
data
Bit Name
IrRxINV

Operation in Asynchronous Mode
1
Start
bit
1 bit
0
Figure 14.5 Data Format in Asynchronous Communication
LSB
D0
Initial
Value
0
All 0
(Example with 8-Bit Data, Parity, Two Stop Bits)
D1
One unit of transfer data (character or frame)
D2
R/W
R/W
—
Transmit/receive data
D3
7 or 8 bits
D4
Description
IrRx Data Invert
This bit specifies the inversion of the logic level in IrRxD
output. When inversion is done, the pulse width of high
state specified by the bits 6 to 4 becomes the pulse
width in low state.
0: Uses the IrRxD input data as it is as receive data.
1: Uses the inverted IrRxD input data as receive data.
Reserved
These bits are always read as 0. It should not be set to
0.
D5
D6
MSB
D7
Parity
bit
1 bit,
or none
0/1
1
Stop bit
1 or
2 bits
1
Idle state
(mark state)
1