DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 529

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse
unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 1 and 0)
that can operate both simultaneously and independently. Figure 11.1 shows a block diagram of the
PPG.
11.1
• 8-bit output data
• Two output groups
• Selectable output trigger signals
• Non-overlapping mode
• Can operate together with the data transfer controller (DTC) and DMA controller (DMAC)
• Inverted output can be set
• Module stop mode can be set
PO7
PO6
PO5
PO4
PO3
PO2
PO1
PO0
[Legend]
PMR:
PCR:
NDERH:
NDERL:
Section 11 Programmable Pulse Generator (PPG)
Features
PPG output mode register
PPG output control register
Next data enable register H
Next data enable register L
Pulse output
pins, group 1
Pulse output
pins, group 0
Compare match signals
Control logic
Figure 11.1 Block Diagram of PPG
NDRH:
NDRL:
PODRH:
PODRL:
PODRH
PODRL
Next data register H
Next data register L
Output data register H
Output data register L
NDERH
PMR
Section 11 Programmable Pulse Generator (PPG)
Rev.1.00 Sep. 08, 2005 Page 479 of 966
NDERL
PCR
NDRH
NDRL
REJ09B0219-0100
Internal
data bus