DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 674

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 14 Serial Communication Interface (SCI, IrDA, CRC)
14.9
14.9.1
Table 14.14 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt request can activate the
DTC or DMAC to allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer
by the DTC or DMAC.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can
activate the DTC or DMAC to allow data transfer. The RDRF flag is automatically cleared to 0 at
data transfer by the DTC or DMAC.
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for
acceptance. However, note that if the TDRE and TEND flags are cleared to 0 simultaneously by
the TXI interrupt processing routine, the SCI cannot branch to the TEI interrupt processing routine
later.
Note that the priority order for interrupts is different between the group of SCI_0, 1, 2, and 4 and
the group of SCI_5 and SCI_6.
Table 14.14 SCI Interrupt Sources (SCI_0, 1, 2, and 4)
Rev.1.00 Sep. 08, 2005 Page 624 of 966
REJ09B0219-0100
Name
ERI
RXI
TXI
TEI
Interrupt Source
Receive error
Receive data full
Transmit data empty TDRE
Transmit end
Interrupt Sources
Interrupts in Normal Serial Communication Interface Mode
Interrupt Flag
ORER, FER, or PER
RDRF
TEND
DTC Activation
Not possible
Possible
Possible
Not possible
DMAC Activation
Not possible
Possible
Possible
Not possible
High
Low
Priority

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