DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 384
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 384 of 1020
- Download datasheet (6Mb)
Section 8 Data Transfer Controller (DTC)
Table 8.10 Number of Cycles Required for Each Execution State
[Legend]
m: Number of wait cycles 0 to 7 (For details, see section 6, Bus Controller (BSC).)
The number of execution cycles is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
8.5.10
The DTC requests the bus mastership to the bus arbiter when an activation request occurs. The
DTC releases the bus after a vector read, transfer information read, a single data transfer, or
transfer information writeback. The DTC does not release the bus during transfer information
read, single data transfer, or transfer information writeback.
8.5.11
The priority of the DTC activation sources over the CPU can be controlled by the CPU priority
level specified by bits CPUP2 to CPUP0 in CPUPCR and the DTC priority level specified by bits
DTCP2 to DTCP0. For details, see section 5, Interrupt Controller.
Rev.1.00 Sep. 08, 2005 Page 334 of 966
REJ09B0219-0100
Object to be Accessed
Bus width
Access cycles
Execution
status
Number of execution cycles = I
Vector read S
Transfer information read S
Transfer information write S
Byte data read S
Word data read S
Longword data read S
Byte data write S
Word data write S
Longword data write S
Internal operation S
DTC Bus Release Timing
DTC Priority Level Control to the CPU
I
L
M
L
M
N
L
M
J
k
On-Chip
RAM
32
1
1
1
1
1
1
1
1
1
1
•
S
I
On-Chip
ROM
32
1
1
1
1
1
1
1
1
1
1
+ Σ (J
•
8
2
2
4
8
2
4
8
S
On-Chip I/O
J
Registers
+ K
16
2
2
2
4
2
2
4
•
S
32
2
2
2
2
2
2
2
K
+ L
1
•
2
8
8
8
2
4
8
2
4
8
S
L
+ M
8
3
12 + 4m
12 + 4m
12 + 4m
3 + m
4 + 2m
12 + 4m
3 + m
4 + 2m
12 + 4m
External Devices
•
S
M
) + N
2
4
4
4
2
2
4
2
2
4
•
S
16
N
3
6 + 2m
6 + 2m
6 + 2m
3 + m
3 + m
6 + 2m
3 + m
3 + m
6 + 2m
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