DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 390

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 Data Transfer Controller (DTC)
8.9.5
When chain transfer is used, clearing of the activation source or DTCER is performed when the
last of the chain of data transfers is executed. At this time, SCI and A/D converter
interrupt/activation sources, are cleared when the DTC reads or writes to the relevant register.
Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the
relevant register is not included in the last chained data transfer, the interrupt or activation source
will be retained.
8.9.6
The transfer information start address to be specified in the vector table should be address 4n. If an
address other than address 4n is specified, the lower 2 bits of the address are regarded as 0s.
The source and destination addresses specified in SAR and DAR, respectively, will be transferred
in the divided bus cycles depending on the address and data size.
8.9.7
When IBCCS = 1 and the DMAC is used, clear the IBCCS bit to 0 and then set to 1 again before
modifying the DTC transfer information in the CPU exception handling routine initiated by a DTC
transfer end interrupt.
8.9.8
The DTC supports big and little endian formats. The endian formats used when transfer
information is written to and when transfer information is read from by the DTC must be the
same.
Rev.1.00 Sep. 08, 2005 Page 340 of 966
REJ09B0219-0100
Chain Transfer
Transfer Information Start Address, Source Address, and Destination Address
Transfer Information Modification
Endian Format