DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 776

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 I
16.4.5
In slave receive mode, the master device outputs the transmit clock and the transmit data, and the
slave device returns an acknowledge signal. Figures 16.11 and 16.12 show the operation timings
in slave receive mode. The reception procedure and operations in slave receive mode are described
below.
1. Set the ICR bit in the corresponding register to 1. Then, set the ICE bit in ICCRA to 1. Set the
2. When the slave address matches in the first frame following detection of the start condition,
3. Read ICDRR every time RDRF is set. If the eighth clock pulse falls while RDRF is 1, SCL is
4. The last byte data is read by reading ICDRR.
Rev.1.00 Sep. 08, 2005 Page 726 of 966
REJ09B0219-0100
(Master output)
(Master output)
ACKBT bit in ICIER and perform other initial settings. Set the MST and TRS bits in ICCRA
to select slave receive mode and wait until the slave address matches.
the slave address outputs the level specified by ACKBT in ICIER to SDA, at the rising of the
ninth clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read).
(Since the read data shows the slave address and R/W, it is not used).
fixed to a low level until ICDRR is read. The change of the acknowledge (ACKBT) setting
before reading ICDRR to be returned to the master device is reflected in the next transmit
frame.
(Slave output)
(Slave output)
processing
ICDRS
ICDRR
RDRF
SDA
SDA
SCL
SCL
User
Slave Receive Operation
2
C Bus Interface2 (IIC2)
[2] Read ICDRR (dummy read)
Figure 16.11 Slave Receive Mode Operation Timing 1
A
9
Bit 7
1
Data 1
Bit 6
2
Bit 5
3
Bit 4
4
Bit 3
5
Bit 2
6
Bit 1
7
Bit 0
8
[2] Read ICDRR
A
9
Data 1
Bit 7
1
Data 2