DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 794

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 17 A/D Converter
3. When A/D conversion of all selected channels is completed, the ADF bit in ADCSR is set to 1.
4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the
Rev.1.00 Sep. 08, 2005 Page 744 of 966
REJ09B0219-0100
ADST
ADF
Channel 0 (AN0)
operation state
Channel 1 (AN1)
operation state
Channel 2 (AN2)
operation state
Channel 3 (AN3)
operation state
ADDRA
ADDRB
ADDRC
ADDRD
If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. A/D conversion of
the first channel in the group starts again.
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the
A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again
from the first channel in the group.
Notes: 1.
2.
Data being converted is ignored.
indicates the timing of instruction execution by software.
Waiting for
conversion
Waiting for conversion
Waiting for conversion
Waiting for conversion
(Scan Mode, Three Channels (AN0 to AN2) Selected)
Figure 17.3 Example of A/D Conversion
Set *
A/D
conver-
sion 1
1
Transfer
A/D conversion consecutive execution
A/D
conver-
sion 2
Waiting for conversion
A/D conversion result 1
A/D
conver-
sion 3
Waiting for conversion
A/D conversion time
A/D
conver-
sion 4
A/D conversion result 2
A/D conversion result 3
A/D
conver-
sion 5
A/D conversion result 4
Waiting for conversion
Waiting for conversion
*
Clear *
2
Waiting for
conversion
1
Clear *
1

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