DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 20

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.4 Operation ........................................................................................................................... 488
11.5 Usage Notes ....................................................................................................................... 499
Section 12 8-Bit Timers (TMR) ........................................................................ 501
12.1 Features.............................................................................................................................. 501
12.2 Input/Output Pins............................................................................................................... 506
12.3 Register Descriptions......................................................................................................... 507
12.4 Operation ........................................................................................................................... 518
12.5 Operation Timing............................................................................................................... 520
12.6 Operation with Cascaded Connection................................................................................ 523
Rev.1.00 Sep. 08, 2005 Page xviii of xlviii
11.3.3 Next Data Registers H, L (NDRH, NDRL) .......................................................... 484
11.3.4 PPG Output Control Register (PCR) .................................................................... 486
11.3.5 PPG Output Mode Register (PMR) ...................................................................... 487
11.4.1 Output Timing ...................................................................................................... 489
11.4.2 Sample Setup Procedure for Normal Pulse Output............................................... 490
11.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output)................ 491
11.4.4 Non-Overlapping Pulse Output............................................................................. 492
11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output............................... 494
11.4.6 Example of Non-Overlapping Pulse Output
11.4.7 Inverted Pulse Output ........................................................................................... 497
11.4.8 Pulse Output Triggered by Input Capture ............................................................. 498
11.5.1 Module Stop Mode Setting ................................................................................... 499
11.5.2 Operation of Pulse Output Pins............................................................................. 499
12.3.1 Timer Counter (TCNT)......................................................................................... 509
12.3.2 Time Constant Register A (TCORA) ................................................................... 509
12.3.3 Time Constant Register B (TCORB).................................................................... 510
12.3.4 Timer Control Register (TCR).............................................................................. 510
12.3.5 Timer Counter Control Register (TCCR) ............................................................. 512
12.3.6 Timer Control/Status Register (TCSR)................................................................. 515
12.4.1 Pulse Output ......................................................................................................... 518
12.4.2 Reset Input............................................................................................................ 519
12.5.1 TCNT Count Timing ............................................................................................ 520
12.5.2 Timing of CMFA and CMFB Setting at Compare Match .................................... 521
12.5.3 Timing of Timer Output at Compare Match......................................................... 521
12.5.4 Timing of Counter Clear by Compare Match ....................................................... 522
12.5.5 Timing of TCNT External Reset*......................................................................... 522
12.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 523
12.6.1 16-Bit Counter Mode ............................................................................................ 523
12.6.2 Compare Match Count Mode ............................................................................... 524
(Example of 4-Phase Complementary Non-Overlapping Pulse Output) .............. 495