DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 932

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 23 List of Registers
Rev.1.00 Sep. 08, 2005 Page 882 of 966
REJ09B0219-0100
Register Name
DMA destination address register_3
DMA offset register_3
DMA transfer count register_3
DMA block size register_3
DMA mode control register_3
DMA address control register_3
DMA module request select register_0
DMA module request select register_1
DMA module request select register_2
DMA module request select register_3
Interrupt priority register A
Interrupt priority register B
Interrupt priority register C
Interrupt priority register E
Interrupt priority register F
Interrupt priority register G
Interrupt priority register H
Interrupt priority register I
Interrupt priority register K
Interrupt priority register L
Interrupt priority register Q
Interrupt priority register R
IRQ sense control register H
IRQ sense control register L
DTC vector base register
Bus width control register
Access state control register
Wait control register A
Wait control register B
Read strobe timing control register
CS assertion period control register
Idle control register
Bus control register1
Bus control register2
Endian control register
Abbreviation
DDAR_3
DOFR_3
DTCR_3
DBSR_3
DMDR_3
DACR_3
DMRSR_0
DMRSR_1
DMRSR_2
DMRSR_3
IPRA
IPRB
IPRC
IPRE
IPRF
IPRG
IPRH
IPRI
IPRK
IPRL
IPRQ
IPRR
ISCRH
ISCRL
DTCVBR
ABWCR
ASTCR
WTCRA
WTCRB
RDNCR
CSACR
IDLCR
BCR1
BCR2
ENDIANCR
32
32
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
8
Number
of Bits
32
32
32
32
8
8
8
8
16
16
32
16
16
16
16
Address
H'FFC64
H'FFC68
H'FFC70
H'FFC74
H'FFC78
H'FFD20
H'FFD21
H'FFD22
H'FFD23
H'FFD40
H'FFD42
H'FFD44
H'FFD48
H'FFD4A
H'FFD4C
H'FFD4E
H'FFD50
H'FFD54
H'FFD56
H'FFD60
H'FFD62
H'FFD68
H'FFD6A
H'FFD84
H'FFD86
H'FFD88
H'FFD8A
H'FFD8C
H'FFD8E
H'FFD90
H'FFD92
H'FFD94
H'FFD95
H'FFC6C
H'FFD80
Module
DMAC_3
DMAC_3
DMAC_3
DMAC_3
DMAC_3
DMAC_3
DMAC_0
DMAC_1
DMAC_2
DMAC_3
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
INTC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
BSC
Data
Width
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2Iφ/3Iφ
Access
Cycles
(Read/Write)
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/2Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ
2Iφ/3Iφ