DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 834

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 Flash Memory (0.18-µm F-ZTAT Version)
(3)
FPEFEQ sets the operating frequency of the CPU. The operating frequency available in this LSI
ranges from 8 MHz to 50 MHz.
Rev.1.00 Sep. 08, 2005 Page 784 of 966
REJ09B0219-0100
Bit
31 to 16 
15 to 0
Bit
Bit Name
Bit
Bit Name
Bit
Bit Name
Bit
Bit Name
Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU)
Bit Name
F15 to F0 
F15
F7
31
23
15
7
Initial
Value

F14
30
22
14
F6
6
R/W

R/W
F13
F5
29
21
13
5
Description
Unused
These bits should be cleared to 0.
Frequency Set
These bits set the operating frequency of the CPU.
When the PLL multiplication function is used, set the
multiplied frequency. The setting value must be
calculated as follows:
1. The operating frequency shown in MHz units must
2. The value multiplied by 100 is converted to the
For example, when the operating frequency of the CPU
is 35.000 MHz, the value is as follows:
1. The number of three decimal places of 35.000 is
2. The formula of 35.00 × 100 = 3500 is converted to
be rounded in a number of three decimal places and
be shown in a number of two decimal places.
binary digit and is written to FPEFEQ (general
register ER0).
rounded.
the binary digit and B'0000 1101 1010 1100
(H'0DAC) is set to ER0.
F12
28
20
12
F4
4
F11
F3
27
19
11
3
F10
26
18
10
F2
2
25
17
F9
F1
9
1
F8
F0
24
16
8
0