DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 166
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 5 Interrupt Controller
Table 5.5
[Legend]
m:
5.6.5
The DTC and DMAC can be activated by an interrupt. In this case, the following options are
available:
• Interrupt request to the CPU
• Activation request to the DTC
• Activation request to the DMAC
• Combination of the above
For details on interrupt requests that can be used to activate the DTC and DMAC, see table 5.2,
section 7, DMA Controller (DMAC), and section 8, Data Transfer Controller (DTC).
Figure 5.6 shows a block diagram of the DTC, DMAC, and interrupt controller.
Rev.1.00 Sep. 08, 2005 Page 116 of 966
REJ09B0219-0100
Symbol
Vector fetch S
Instruction fetch S
Stack manipulation S
Number of wait cycles in an external device access.
DTC and DMAC Activation by Interrupt
Number of Execution States in Interrupt Handling Routine
h
I
K
On-Chip
Memory
1
1
1
2-State
Access
8
4
8
8-Bit Bus
Object of Access
3-State
Access
12 + 4m
6 + 2m
12 + 4m
External Device
2-State
Access
4
2
4
16-Bit Bus
3-State
Access
6 + 2m
3 + m
6 + 2m
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