DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 137

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.1
• Two interrupt control modes
• Priority can be assigned by the interrupt priority register (IPR)
• Independent vector addresses
• Thirteen external interrupts
• DTC and DMAC control
• CPU priority control function
Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the
interrupt control register (INTCR).
IPR provides for setting interrupt priory. Eight levels can be set for each module for all
interrupts except for the interrupt requests listed below. The following seven interrupt requests
are given priority of 8, therefore they are accepted at all times.
 NMI
 Illegal instructions
 Trace
 Trap instructions
 CPU address error
 DMA address error (occurred in the DTC and DMAC)
 Sleep interrupt
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
detection can be selected for NMI. Falling edge, rising edge, or both edge detection, or level
sensing, can be selected for IRQ11 to IRQ0.
DTC and DMAC can be activated by means of interrupts.
The priority levels can be assigned to the CPU, DTC, and DMAC. The priority level of the
CPU can be automatically assigned on an exception generation. Priority can be given to the
CPU interrupt exception handling over that of the DTC and DMAC transfer.
Features
Section 5 Interrupt Controller
Rev.1.00 Sep. 08, 2005 Page 87 of 966
Section 5 Interrupt Controller
REJ09B0219-0100