DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 256

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
When consecutively reading from the same area connected to a peripheral LSI whose data hold
time is long, data outputs from the peripheral LSI and this LSI may conflict. Inserting the chip
select assertion period extension cycle after the access cycle can avoid the data conflict.
Figure 6.35 shows an example of the operation. In the figure, both bus cycles A and B are read
access cycles to the address/data multiplexed I/O space. An example of the data conflict is shown
in (a), and an example of avoiding the data conflict by the CS assertion period extension cycle in
(b).
Rev.1.00 Sep. 08, 2005 Page 206 of 966
REJ09B0219-0100
B
Address bus
CS
AH
RD
Data bus
B
Address bus
CS
AH
RD
Data bus
Figure 6.35 Consecutive Read Accesses to Same Area
(a) Without CS assertion period extension cycle (CSXTn = 0)
(b) With CS assertion period extension cycle (CSXTn = 1)
(Address/Data Multiplexed I/O Space)
Bus cycle A
Bus cycle A
Data hold time is long.
Bus cycle B
Data conflict
Bus cycle B