DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 13

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.6
4.7
4.8
4.9
Section 5 Interrupt Controller ..............................................................................87
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
4.5.1
4.5.2
Interrupts.............................................................................................................................. 82
4.6.1
4.6.2
Instruction Exception Handling ........................................................................................... 83
4.7.1
4.7.2
Stack Status after Exception Handling................................................................................. 85
Usage Note........................................................................................................................... 86
Features................................................................................................................................ 87
Input/Output Pins ................................................................................................................. 89
Register Descriptions ........................................................................................................... 89
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
Interrupt Sources................................................................................................................ 103
5.4.1
5.4.2
5.4.3
Interrupt Exception Handling Vector Table....................................................................... 105
Interrupt Control Modes and Interrupt Operation .............................................................. 110
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
CPU Priority Control Function Over DTC and DMAC..................................................... 119
Usage Notes ....................................................................................................................... 122
5.8.1
5.8.2
5.8.3
5.8.4
Address Error Source.............................................................................................. 80
Address Error Exception Handling ......................................................................... 81
Interrupt Sources..................................................................................................... 82
Interrupt Exception Handling ................................................................................. 83
Trap Instruction....................................................................................................... 83
Exception Handling by Illegal Instruction .............................................................. 84
Interrupt Control Register (INTCR) ....................................................................... 90
CPU Priority Control Register (CPUPCR) ............................................................. 91
Interrupt Priority Registers A to C, E to I, K, L, Q, and R
(IPRA to IPRC, IPRE to IPRI, IPRK, IPRL, IPRQ, and IPRR) ............................. 92
IRQ Enable Register (IER) ..................................................................................... 95
IRQ Sense Control Registers H and L (ISCRH, ISCRL)........................................ 96
IRQ Status Register (ISR)..................................................................................... 101
Software Standby Release IRQ Enable Register (SSIER) .................................... 102
External Interrupts ................................................................................................ 103
Internal Interrupts ................................................................................................. 104
Sleep Interrupt....................................................................................................... 104
Interrupt Control Mode 0 ...................................................................................... 110
Interrupt Control Mode 2 ...................................................................................... 112
Interrupt Exception Handling Sequence ............................................................... 114
Interrupt Response Times ..................................................................................... 115
DTC and DMAC Activation by Interrupt ............................................................. 116
Conflict between Interrupt Generation and Disabling .......................................... 122
Instructions that Disable Interrupts ....................................................................... 123
Times when Interrupts are Disabled ..................................................................... 123
Interrupts during Execution of EEPMOV Instruction........................................... 123
Rev.1.00 Sep. 08, 2005 Page xi of xlviiil