DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 117
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 117 of 1020
- Download datasheet (6Mb)
3.3.4
The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on-
chip ROM is enabled.
The initial bus width mode immediately after a reset is eight bits, with 8-bit access to all areas.
Ports D, E, and F function as input ports, but they can be used as an address bus by specifying the
data direction register (DDR) for each port. For details, see section 9, I/O Ports. Port H functions
as a data bus, and parts of ports A and B function as bus control signals. However, if any area is
designated as a 16-bit access space by the bus controller, the bus width mode switches to 16 bits,
and ports H and I function as a data bus.
3.3.5
The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on-
chip ROM is enabled.
In the initial state, all areas are designated to 8-bit access space and all I/O ports can be used as
general input/output ports. The external address space cannot be accessed in the initial state, but
setting the EXPE bit in the system control register (SYSCR) to 1 enables the external address
space. After the external address space is enabled, ports D, E, and F can be used as an address
output bus and ports H and I as a data bus by specifying the data direction register (DDR) for each
port. For details, see section 9, I/O Ports.
Mode 6
Mode 7
Rev.1.00 Sep. 08, 2005 Page 67 of 966
Section 3 MCU Operating Modes
REJ09B0219-0100
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