DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 535

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• NDRL
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3 to 0
Bit
7 to 4
3
2
1
0
If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the
same address and can be accessed at one time, as shown below.
If pulse output groups 0 and 1 have different output triggers, the upper four bits and lower four
bits are mapped to different addresses as shown below.
Bit Name
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
Bit Name
NDR7
NDR6
NDR5
NDR4

Bit Name

NDR3
NDR2
NDR1
NDR0
Initial
Value
0
0
0
0
0
0
0
0
Initial
Value
0
0
0
0
All 1
Initial
Value
All 1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

R/W

R/W
R/W
R/W
R/W
Description
Next Data Register 7 to 0
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Description
Next Data Register 7 to 4
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Reserved
These bits are always read as 1 and cannot be
modified.
Description
Reserved
These bits are always read as 1 and cannot be
modified.
Next Data Register 3 to 0
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Section 11 Programmable Pulse Generator (PPG)
Rev.1.00 Sep. 08, 2005 Page 485 of 966
REJ09B0219-0100