DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 822

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 Flash Memory (0.18-µm F-ZTAT Version)
Rev.1.00 Sep. 08, 2005 Page 772 of 966
REJ09B0219-0100
Bit
7
6
5
4
3 to 1
Bit Name



FLER

Initial
Value
1
0
0
0
All 0
R/W
R
R
R
R
R
Description
Reserved
These are read-only bits and cannot be modified.
Flash Memory Error
Indicates that an error has occurred during programming
or erasing the flash memory. When this bit is set to 1,
the flash memory enters the error protection state.
When this bit is set to 1, high voltage is applied to the
internal flash memory. To reduce the damage to the
flash memory, the reset must be released after the reset
input period (period of RES = 0) of at least 100 µs.
0: Flash memory operates normally (Error protection is
[Clearing condition]
•
1: An error occurs during programming/erasing flash
[Setting conditions]
•
•
•
•
Reserved
These are read-only bits and cannot be modified.
invalid)
At a power-on reset
memory (Error protection is valid)
When an interrupt, such as NMI, occurs during
programming/erasing.
When the flash memory is read during
programming/erasing (including a vector read and
an instruction fetch).
When the SLEEP instruction is executed during
programming/erasing (including software standby
mode).
When a bus master other than the CPU, such as the
DMAC and DTC, obtains bus mastership during
programming/erasing.