DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 769

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.4.2
In I
data, and the slave device return an acknowledge signal. Figures 16.5 and 16.6 show the operating
timings in master transmit mode. The transmission procedure and operations in master transmit
mode are described below.
1. Set the ICR bit in the corresponding register to 1. Set the ICE bit in ICCRA to 1. Set the WAIT
2. Read the BSSY flag in ICCRB to confirm that the bus is free. Set the MST and TRS bits in
3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte shows
4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1
5. The transmit data after the second byte is written to ICDRT every time TDRE is set.
6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last
7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
2
bit in ICMR and the CKS3 to CKS0 bits in ICCRA to 1. (initial setting)
ICCRA to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using the MOV
instruction. (The start condition is issued.) This generates the start condition.
the slave address and R/W) to ICDRT. After this, when TDRE is automatically cleared to 0,
data is transferred from ICDRT to ICDRS. TDRE is set again.
at the rising of the ninth transmit clock pulse. Read the ACKBR bit in ICIER to confirm that
the slave device has been selected. Then, write the second byte data to ICDRT. When ACKBR
is 1, the slave device has not been acknowledged, so issue a stop condition. To issue the stop
condition, write 0 to BBSY and SCP using the MOV instruction. SCL is fixed to a low level
until the transmit data is prepared or the stop condition is issued.
byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR is 1) from the
receive device while CKE in ICIER is 1. Then, issue the stop condition to clear TEND or
NACKF.
C bus format master transmit mode, the master device outputs the transmit clock and transmit
Master Transmit Operation
Rev.1.00 Sep. 08, 2005 Page 719 of 966
Section 16 I
2
C Bus Interface2 (IIC2)
REJ09B0219-0100