DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 745

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.8
15.8.1
DMA transfer can be performed for endpoints 1 and 2 in this module. Note that word or longword
data cannot be transferred.
When endpoint 1 holds at least one byte of valid receive data, a DMA request for endpoint 1 is
generated. When endpoint 2 holds no valid data, a DMA request for endpoint 2 is generated.
If the DMA transfer is enabled by setting the EP1DMAE bit in the DMA transfer setting register
to 1, zero-length data reception at endpoint 1 is ignored. When the DMA transfer is enabled, the
RDFN bit for EP1 and PKTE bit for EP2 do not need to be set to 1 in TRG (note that the PKTE bit
must be set to 1 when the transfer data is less than the maximum number of bytes). When all the
data received at EP1 is read, the FIFO automatically enters the EMPTY state. When the maximum
number of bytes (64 bytes) are written to the EP2 FIFO, the FIFO automatically enters the FULL
state, and the data in the FIFO can be transmitted (see figures 15.20 and 15.21).
15.8.2
When the data received at EP1 is transferred by the DMAC, the USB function module
automatically performs the same processing as writing 1 to the RDFN bit in TRG if the currently
selected FIFO becomes empty. Accordingly, in DMA transfer, do not write 1 to the RDFN bit in
TRG. If the user writes 1 to the RDFN bit in DMA transfer, correct operation cannot be
guaranteed.
Figure 15.20 shows an example of receiving 150 bytes of data from the host. In this case, internal
processing which is the same as writing 1 to the RDFN bit in TRG is automatically performed
three times. This internal processing is performed when the currently selected data FIFO becomes
empty. Accordingly, this processing is automatically performed both when 64-byte data is sent
and when data less than 64 bytes is sent.
DMA Transfer
Overview
DMA Transfer for Endpoint 1
64 bytes
Figure 15.20 RDFN Bit Operation for EP1
RDFN
(Automatically
performed)
64 bytes
RDFN
(Automatically
performed)
Rev.1.00 Sep. 08, 2005 Page 695 of 966
Section 15 USB Function Module (USB)
22 bytes
RDFN
(Automatically
performed)
REJ09B0219-0100