DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 332

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 7 DMA Controller (DMAC)
7.5.9
Figure 7.23 shows an examples of signal timing of a basic bus cycle. In figure 7.23, data is
transferred in words from the 16-bit 2-state access space to the 8-bit 3-state access space. When
the bus mastership is passed from the DMAC to the CPU, data is read from the source address and
it is written to the destination address. The bus is not released between the read and write cycles
by other bus requests. DMAC bus cycles follows the bus controller settings.
Rev.1.00 Sep. 08, 2005 Page 282 of 966
REJ09B0219-0100
B
Address bus
RD
LHWR
LLWR
DMA Basic Bus Cycle
High
CPU cycle
Figure 7.23 Example of Bus Timing of DMA Transfer
Source address
T
1
T
2
T
1
DMAC cycle (one word transfer)
T
2
Destination address
T
3
T
1
T
2
T
3
CPU cycle

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