DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 379

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.5.6
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area by the DTS bit in MRB.
The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). When the transfer of one
block ends, the block size counter (CRAL) and address register (SAR when DTS = 1 or DAR
when DTS = 0) specified as the block area is restored to the initial state. The other address register
is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. When
the specified number of transfers ends, an interrupt is requested to the CPU.
Table 8.8 lists the register function in block transfer mode. Figure 8.9 shows the memory map in
block transfer mode.
Table 8.8
Note:
Register Function
SAR
DAR
CRAH
CRAL
CRB
*
Block Transfer Mode
Source address
Destination address
Block size storage
Block size counter
Block transfer counter
Transfer information writeback is skipped.
Register Function in Block Transfer Mode
SAR
(When Transfer Destination is Specified as Block Area)
Transfer source data area
Figure 8.9 Memory Map in Block Transfer Mode
Nth block
1st block
:
:
Written Back Value
DTS =0: Incremented/decremented/fixed*
DTS = 1: SAR initial value
DTS = 0: DAR initial value
DTS =1: Incremented/decremented/fixed*
CRAH
CRAH
CRB − 1
Transfer
Transfer destination data area
(specified as block area)
Block area
Section 8 Data Transfer Controller (DTC)
Rev.1.00 Sep. 08, 2005 Page 329 of 966
DAR
REJ09B0219-0100