DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 19

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.4 Operation ........................................................................................................................... 435
10.5 Interrupt Sources................................................................................................................ 461
10.6 DTC Activation.................................................................................................................. 463
10.7 DMAC Activation.............................................................................................................. 463
10.8 A/D Converter Activation.................................................................................................. 463
10.9 Operation Timing............................................................................................................... 464
10.10 Usage Notes ....................................................................................................................... 472
Section 11 Programmable Pulse Generator (PPG) ............................................479
11.1 Features.............................................................................................................................. 479
11.2 Input/Output Pins ............................................................................................................... 480
11.3 Register Descriptions ......................................................................................................... 480
10.3.5 Timer Status Register (TSR)................................................................................. 429
10.3.6 Timer Counter (TCNT)......................................................................................... 432
10.3.7 Timer General Register (TGR) ............................................................................. 432
10.3.8 Timer Start Register (TSTR) ................................................................................ 433
10.3.9 Timer Synchronous Register (TSYR)................................................................... 434
10.4.1 Basic Functions..................................................................................................... 435
10.4.2 Synchronous Operation......................................................................................... 441
10.4.3 Buffer Operation ................................................................................................... 443
10.4.4 Cascaded Operation .............................................................................................. 447
10.4.5 PWM Modes ......................................................................................................... 449
10.4.6 Phase Counting Mode........................................................................................... 454
10.9.1 Input/Output Timing ............................................................................................. 464
10.9.2 Interrupt Signal Timing......................................................................................... 468
10.10.1 Module Stop Mode Setting ................................................................................... 472
10.10.2 Input Clock Restrictions ....................................................................................... 472
10.10.3 Caution on Cycle Setting ...................................................................................... 473
10.10.4 Conflict between TCNT Write and Clear Operations........................................... 473
10.10.5 Conflict between TCNT Write and Increment Operations ................................... 474
10.10.6 Conflict between TGR Write and Compare Match............................................... 474
10.10.7 Conflict between Buffer Register Write and Compare Match .............................. 475
10.10.8 Conflict between TGR Read and Input Capture ................................................... 475
10.10.9 Conflict between TGR Write and Input Capture .................................................. 476
10.10.10 Conflict between Buffer Register Write and Input Capture................................ 477
10.10.11 Conflict between Overflow/Underflow and Counter Clearing ........................... 477
10.10.12 Conflict between TCNT Write and Overflow/Underflow .................................. 478
10.10.13 Interrupts and Module Stop Mode ...................................................................... 478
11.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ......................................... 481
11.3.2 Output Data Registers H, L (PODRH, PODRL)................................................... 482
Rev.1.00 Sep. 08, 2005 Page xvii of xlviiil