DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 693

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15.3.2
IFR1, together with interrupt flag registers 0 and 2 (IFR0 and IFR2), indicates interrupt status
information required by the application. When an interrupt source is generated, the corresponding
bit is set to 1. And then this bit, in combination with interrupt enable register 1 (IER1), generates
an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
Bit
2
1
0
Bit
7
6
5
4
Bit
Bit Name
Initial Value
R/W
Interrupt Flag Register 1 (IFR1)
Bit Name
EP0oTS
EP0iTR
EP0iTS
Bit Name
R
7
0
Initial
Value
0
0
0
Initial
Value
0
0
0
0
R
6
0
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
5
0
EP0o Receive Complete
EP0i Transfer Request
EP0i Transmit Complete
Description
This bit is set to 1 when endpoint 0 receives data from
the host successfully, stores the data in the FIFO
buffer, and returns an ACK handshake to the host.
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 0 is
received from the host. A NACK handshake is returned
to the host until data is written to the FIFO buffer and
packet transmission is enabled.
This bit is set when data is transmitted to the host from
endpoint 0 and an ACK handshake is returned.
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
R
4
0
VBUS MN
R
3
0
Rev.1.00 Sep. 08, 2005 Page 643 of 966
Section 15 USB Function Module (USB)
EP3 TR
R/W
2
0
EP3 TS
R/W
1
0
REJ09B0219-0100
VBUSF
R/W
0
0

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