DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 235

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.7
The byte control SRAM interface is a memory interface for outputting a byte select strobe during
a read or a write bus cycle. This interface has 16-bit data input/output pins and can be connected to
the SRAM that has the upper byte select and the lower byte select strobes such as UB and LB.
The operation of the byte control SRAM interface is the same as the basic bus interface except
that: the byte select strobes (LUB and LLB) are output from the write strobe output pins (LHWR
and LLWR), respectively; the read strobe (RD) negation timing is a half cycle earlier than that in
the case where RDNn = 0 in the basic bus interface regardless of the RDNCR settings; and the
RD/WR signal is used as write enable.
6.7.1
Byte control SRAM interface can be specified for areas 0 to 7. Each area can be specified as byte
control SRAM interface by setting bits BCSELn (n = 0 to 7) in SRAMCR. For the area specified
as burst ROM interface or address/data multiplexed I/O interface, the SRAMCR setting is invalid
and byte control SRAM interface cannot be used.
6.7.2
The bus width of the byte control SRAM space can be specified as 16-bit byte control SRAM
space according to bits ABWHn and ABWLn (n = 0 to 7) in ABWCR. The area specified as 8-bit
access space cannot be specified as the byte control SRAM space.
For the 16-bit byte control SRAM space, data bus (D15 to D0) is valid.
Access size and data alignment are the same as the basic bus interface. For details, see section
6.5.6, Endian and Data Alignment.
Byte Control SRAM Interface
Byte Control SRAM Space Setting
Data Bus
Rev.1.00 Sep. 08, 2005 Page 185 of 966
Section 6 Bus Controller (BSC)
REJ09B0219-0100