DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 695

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15.3.4
ISR0 selects the vector numbers of the interrupt requests indicated in interrupt flag register 0
(IFR0). If the USB issues an interrupt request to the INTC when a bit in ISR0 is cleared to 0, the
interrupt corresponding to the bit will be USBINTN2. If the USB issues an interrupt request to the
INTC when a bit in ISR0 is set to 1, the corresponding interrupt will be USBINTN3.
Bit
5
4
3
2
1
0
Bit
Bit Name
Initial Value
R/W
Interrupt Select Register 0 (ISR0)
Bit Name
SURSS
SURSF
CFDN
SETC
SETI
BRST
R/W
7
0
EP1 FULL
Initial
Value
0
0
0
0
0
0
R/W
6
0
R/W
R/W
R/W
R
R/W
R/W
R
EP2 TR
R/W
5
0
Description
Suspend/Resume Detection
End Point Information Load End
Set_Configuration Command Detection
Set_Interface Command Detection
Suspend/Resume Status
This is a status bit that describes bus state.
0: Normal state
1: Suspended state
This bit is a status bit and generates no interrupt
request.
This bit is set to 1 when the state changed from normal
to suspended state or vice versa. The corresponding
interrupt output is RESUME, USBINTN2, and
USBINTN3.
This bit is set to 1 when writing data in the endpoint
information register to the EPIR register ends (load
end). This module starts the USB operation after the
endpoint information is completely set.
Reserved
This bit is always read as 0. The write value should
always be 0.
When the Set_Configuration command is detected, this
bit is set to 1.
When the Set_Interface command is detected, this bit
is set to 1.
EP2 EMPTY
R/W
4
0
SETUP TS
R/W
3
0
Rev.1.00 Sep. 08, 2005 Page 645 of 966
Section 15 USB Function Module (USB)
EP0o TS
R/W
2
0
EP0i TR
R/W
1
0
REJ09B0219-0100
EP0i TS
R/W
0
0

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