DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 666

IC H8SX/1654 MCU FLASH 120TQFP

DF61654N50FTV

Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61654N50FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 14 Serial Communication Interface (SCI, IrDA, CRC)
TDRE
TEND
FER/ERS
Note that the TEND flag is set in different timings depending on the GM bit setting in SMR.
Figure 14.30 shows the TEND flag set timing.
Rev.1.00 Sep. 08, 2005 Page 616 of 966
REJ09B0219-0100
I/O data
TXI
(TEND interrupt)
Ds
[Legend]
Ds:
D0 to D7: Data bits
Dp:
DE:
Transfer from TDR to TSR
Figure 14.29 Data Re-Transfer Operation in SCI Transmission Mode
GM = 0
GM = 1
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Figure 14.30 TEND Flag Set Timing during Transmission
nth transfer frame
Start bit
Parity bit
Error signal
Ds
D0
D1
[1]
D2
[2]
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
D3
Transfer from TDR to TSR
11.0 etu
12.5 etu
D4
Retransfer frame
D5
D6
D7
Dp
(DE)
[3]
[4]
Guard time
DE
Ds D0 D1 D2 D3 D4
Transfer from TDR to TSR
transfer frame
(n + 1) th

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