DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 702

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 USB Function Module (USB)
15.3.13 EP1 Data Register (EPDR1)
EPDR1 is a 128-byte receive FIFO buffer for endpoint 1. EPDR1 has a dual-buffer configuration,
and has a capacity of twice the maximum packet size. When one packet of data is received
successfully, EP1FULL in interrupt flag register 0 is set, and the number of receive bytes is
indicated in the EP1 receive data size register. After the data has been read, the buffer that was
read is enabled to receive data again by writing 1 to the EP1RDFN bit in the trigger register. The
receive data in this FIFO buffer can be transferred by DMA. This FIFO buffer can be initialized
by means of EP1CLR in the FCLR register.
15.3.14 EP2 Data Register (EPDR2)
EPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. EPDR2 has a dual-buffer configuration,
and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO
buffer and EP2PKTE in the trigger register is set, one packet of transmit data is fixed, and the
dual-FIFO buffer is switched over. The transmit data for this FIFO buffer can be transferred by
DMA. This FIFO buffer can be initialized by means of EP2CLR in the FCLR register.
Rev.1.00 Sep. 08, 2005 Page 652 of 966
REJ09B0219-0100
Bit
7 to 0
Bit
7 to 0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Name
D7 to D0
Bit Name
D7 to D0
Undefined
D7
D7
W
R
7
0
7
Undefined
Initial
Value
Undefined W
Initial
Value
All 0
D6
D6
W
R
6
0
6
Undefined
R/W
R
R/W
D5
D5
W
R
5
0
5
Description
Data register for endpoint 1 transfer
Description
Data register for endpoint 2 transfer
Undefined
D4
D4
W
R
4
0
4
Undefined
D3
D3
W
R
3
0
3
Undefined
D2
D2
W
R
2
0
2
Undefined
D1
D1
W
R
1
0
1
Undefined
D0
D0
W
R
0
0
0