DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 528

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 16-Bit Timer Pulse Unit (TPU)
10.10.12 Conflict between TCNT Write and Overflow/Underflow
If an overflow/underflow occurs due to increment/decrement in the T2 state of a TCNT write
cycle, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set.
Figure 10.54 shows the operation timing when there is conflict between TCNT write and
overflow.
10.10.13 Interrupts and Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore
be disabled before entering module stop mode.
Rev.1.00 Sep. 08, 2005 Page 478 of 966
REJ09B0219-0100
Figure 10.53 Conflict between Overflow and Counter Clearing
P
TCNT input
clock
TCNT
Counter clear
signal
TGF flag
TCFV flag
Figure 10.54 Conflict between TCNT Write and Overflow
P
Address
Write
TCNT
TCFV flag
H'FFFF
Disabled
H'FFFF
TGR write cycle
T
TCNT address
1
T
2
H'0000
M
TCNT write data