DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 160

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 5 Interrupt Controller
5.6
The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt
control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt
control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control
mode 0 and interrupt control mode 2.
Table 5.3
5.6.1
In interrupt control mode 0, interrupt requests except for NMI and sleep interrupt are masked by
the I bit in CCR of the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in
this case.
1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, the
2. If the I bit in CCR is set to 1, NMI and sleep interrupt is accepted, and other interrupt requests
3. For multiple interrupt requests, the interrupt controller selects the interrupt request with the
4. When the CPU accepts the interrupt request, it starts interrupt exception handling after
5. The PC and CCR contents are saved to the stack area during the interrupt exception handling.
6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI and sleep interrupt.
Rev.1.00 Sep. 08, 2005 Page 110 of 966
REJ09B0219-0100
Interrupt
Control
Mode
0
2
interrupt request is sent to the interrupt controller.
are held pending. If the I bit is cleared to 0, an interrupt request is accepted.
highest priority, sends the request to the CPU, and holds other interrupt requests pending.
execution of the current instruction has been completed.
The PC contents saved on the stack is the address of the first instruction to be executed after
returning from the interrupt handling routine.
Interrupt Control Modes and Interrupt Operation
Interrupt Control Mode 0
Interrupt Control Modes
Priority
Setting
Register
Default
IPR
Interrupt
Mask Bit
I
I2 to I0
Description
The priority levels of the interrupt sources are fixed
default settings.
The interrupts except for NMI and sleep interrupt is
masked by the I bit.
Eight priority levels can be set for interrupt sources
except for NMI and sleep interrupt with IPR.
8-level interrupt mask control is performed by bits I2 to
I0.