DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 88

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 2 CPU
[Legend]
d:
S:
D:
SD:
S/D:
S:4:
Notes: 1. Only @aa:16 is available.
Rev.1.00 Sep. 08, 2005 Page 38 of 966
REJ09B0219-0100
Classifi-
cation
Bit
manipu-
lation
Branch
System
control
d:16 or d:32
Can be specified as a source operand.
Can be specified as a destination operand.
Can be specified as either a source or destination operand or both.
Can be specified as either a source or destination operand.
4-bit immediate data can be specified as a source operand.
2. @ERn+ as a source operand and @−ERn as a destination operand
3. Specified by ER5 as a source address and ER6 as a destination address for data
4. Size of data to be added with a displacement
5. Only @ERn− is available
6. When the number of bits to be shifted is 1, 2, 4, 8, or 16
7. When the number of bits to be shifted is specified by 5-bit immediate data or a general
8. Size of data to specify a branch condition
9. Byte when immediate or register direct, otherwise, word
10. Only @ERn+ is available
11. Only @−ERn is available
12. Not available in this LSI.
Instruction
BFLD
BFST
BRA/BS, BRA/BC*
BSR/BS, BSR/BC*
LDC
(CCR, EXR)
LDC
(VBR, SBR)
STC
(CCR, EXR)
STC
(VBR, SBR)
ANDC, ORC,
XORC
SLEEP
NOP
transfer.
register
8
8
Size
B
B
B
B
B/W*
L
B/W*
L
B
—
—
9
9
#xx
S
S
Rn
D
S
S
S
D
D
@ERn @(d,ERn)
S
D
S
S
S
D
S
D
Addressing Mode
@(d,
RnL.B/
Rn.W/
ERn.L)
@−ERn/
@ERn+/
@ERn−/
@+ERn
S*
D*
10
11
@aa:8
S
D
S
S
@aa:16/
@aa:32
S
D
S
S
S
D
—
O
O