DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 142
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 5 Interrupt Controller
Note:
5.3.3
IPR sets priory (levels 7 to 0) for interrupts other than NMI and sleep interrupt.
Setting a value in the range from B'000 to B'111 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4,
and 2 to 0 assigns a priority level to the corresponding interrupt. For the correspondence between
the interrupt sources and the IPR settings, see table 5.2.
Rev.1.00 Sep. 08, 2005 Page 92 of 966
REJ09B0219-0100
Bit
2
1
0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
*
Bit Name
CPUP2
CPUP1
CPUP0
Interrupt Priority Registers A to C, E to I, K, L, Q, and R
(IPRA to IPRC, IPRE to IPRI, IPRK, IPRL, IPRQ, and IPRR)
When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits
cannot be modified.
15
R
R
0
7
0
Initial
Value
0
0
0
IPR14
IPR6
R/W
R/W
14
1
6
1
R/W
R/(W)*
R/(W)*
R/(W)*
IPR13
IPR5
R/W
R/W
13
1
5
1
Description
CPU Priority Level 2 to 0
These bits set the CPU priority level. When the
CPUPCE is set to 1, the CPU priority control function
over the DTC and DMAC becomes valid and the priority
of CPU processing is assigned in accordance with the
settings of bits CPUP2 to CPUP0.
000: Priority level 0 (lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (highest)
IPR12
IPR4
R/W
R/W
12
1
4
1
11
R
R
3
0
0
IPR10
IPR2
R/W
R/W
10
1
2
1
IPR9
IPR1
R/W
R/W
9
1
1
1
IPR8
IPR0
R/W
R/W
8
1
0
1
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